PIC18F83J11T-I/PT【PDF 3/332 页】IC PIC MCU FLASH 4KX16 80TQFP

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PIC18F85J11 FAMILY

DS39774D-page 100

2010 Microchip Technology Inc.

8.1

External Memory Bus Control

The operation of the interface is controlled by the

MEMCON register (Register 8-1). This register is

available in all Program Memory modes except Micro-

controller mode. In this mode, the register is disabled

and cannot be written to.

The EBDIS bit (MEMCON<7>) controls the operation

of the bus and related port functions. Clearing EBDIS

enables the interface and disables the I/O functions of

the ports, as well as any other functions multiplexed to

those pins. Setting the bit enables the I/O ports and

other functions, but allows the interface to override

everything else on the pins when an external memory

operation is required. By default, the external bus is

always enabled and disables all other I/O.

The operation of the EBDIS bit is also influenced by the

Program Memory mode being used. This is discussed

in more detail in Section 8.5 “Program Memory

Modes and the External Memory Bus”.

The WAIT bits allow for the addition of Wait states to

external memory operations. The use of these bits is

discussed in Section 8.3 “Wait States”.

The WM bits select the particular operating mode used

when the bus is operating in 16-Bit Data Width mode.

These are discussed in more detail in Section 8.6

“16-Bit Data Width Modes”. These bits have no effect

when an 8-Bit Data Width mode is selected.

REGISTER 8-1:

MEMCON: EXTERNAL MEMORY BUS CONTROL REGISTER

R/W-0

U-0

R/W-0

U-0

R/W-0

EBDIS

—WAIT1

WAIT0

—

—WM1

WM0

bit 15

bit 8

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

EBDIS: External Bus Disable bit

= External bus is enabled when microcontroller accesses external memory; otherwise, all external

bus drivers are mapped as I/O ports

= External bus is always enabled, I/O ports are disabled

bit 6

Unimplemented: Read as ‘0’

bit 5-4

WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits

= Table reads and writes will wait 0 TCY

= Table reads and writes will wait 1 TCY

= Table reads and writes will wait 2 TCY

= Table reads and writes will wait 3 TCY

bit 3-2

Unimplemented: Read as ‘0’

bit 1-0

WM<1:0>: TBLWT Operation with 16-Bit Data Bus Width Select bits

= Word Write mode: TABLAT0 and TABLAT1 word output; WRH active when TABLAT1 written

= Byte Select mode: TABLAT data copied on both MSB and LSB; WRH and (UB or LB) will activate

= Byte Write mode: TABLAT data copied on both MSB and LSB; WRH or WRL will activate

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